Stable and deterministic kernel with a tiny memory and instruction footprint ideal for simulation environments
Extremely fast test generation and execution to cover a large amount of verification space in a small amount of time
Run the exactly same portable stimulus on simulation, FPGA prototype, emulation or silicon without any change
Extensive hardware support including ARMv8, RISC-V and USB. Check the section below for details
Generates extremely tight sequences of code for faster closure on coverage
Interspersed directed and random testing for better coverage under different levels of stress
Configuration file based input to control kernel setup, test generation and execution
Special kernel and library APIs for design verification available to test developers to write stimulus generators
Clock, power, memory and interrupt management support provided by kernel to the test generators and device drivers
Support for standard verification algorithms is available with the library of test stimulus
Shift-left the design verification by using the same tool on simulation, emulation, FPGA prototypes and silicon; Test stimulus scales automatically on different hardware/software configurations; Improved throughput for test development and debug; Save on cost, time and resources spent on redundant verification
Test all IPs at once by concurrently enabling traffic; Covers all the IP cross-products thoroughly and throttle the system to its maximum; Advanced CPU and IO scheduling mechanisms in kernel ensures that the coverage goals are met in least possible time
Diverse test development mechanisms supported in the tool; Bias based mechanism to generate traffic for random testing needs; Supports a framework for development of directed tests using snippets of ASM like low level programming language; Allows C++ based test development for scenarios which require complex programming constructs
Large library of test stimulus shipped with the tool; Coverage for common test scenarios like message passing, memory coherency and consistency, cacheline sharing between IPs, pipeline hazards etc. and device drivers for multiple IPs provided in the library; The library of test stimulus ensures easy ramp into verification readiness
User friendly and intuitive design makes the tool usage easy for engineers. Specially designed user interface to make complex test specification easy; Easily interpretable test report file and debug logs with verbose information for manual/automated test intent analysis and failure debug; Extended documentation, FAQs and support manuals;
Ease of failure debug facilitated by a host of tool features; Consistent execution environment and reliable failure reproduction makes it easy to recreate a post-si failure in emulation or pre-si; Debug hooks and mechanisms implemented in tool which allow rapid failure debug and resolution; Mechanism to incrementally reduce the test content from failure point for quick triage;
Add custom extensions in the tool for proprietary IPs developed by companies; Test content management layer lets the native features to be randomized effectively with the new extensions developed; C++ based API makes it easy to develop standalone device drivers;
Multiple modes of execution available for different verification environments; Slower simulations can execute a mode where only the test is run on target and setup/check is done offline; On silicon, all the components can be run on the target for maximum test throughput