Valtrix will participate in the 8th RISC-V workshop at Barcelona, Spain in May 2018. Co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set.
The high level details of the two Valtrix poster presentations are given below -
Authors: Shubhodeep Roy Choudhury and Shajid Thiruvathodi from Valtrix Technologies Pvt. Ltd. and Vaidyanathan Seetharaman, Matt Cockrell, Jon Michelson and Jason Redgrave from Google Inc.
Google uses the PULPino RISC-V core RISCY as a job scheduling and dispatch mechanism for a hardware accelerator (similar to a GPU controller). This requires full compliance with the RISC- V RV32I base integer instruction set, standard extensions for integer multiplication and division (‘M’) and compressed instructions (‘C’), and capability to handle interrupts from multiple sources. We used STING, a software-driven verification solution for RISC-V based CPU/SoC implementations, to verify the architectural compliance and functionality of the RISCY core. This verification effort helped uncover 30 RTL, documentation, and toolchain issues in the relatively mature RISCY implementation.
Authors: Shubhodeep Roy Choudhury and Shajid Thiruvathodi from Valtrix Technologies Pvt. Ltd.
The concept of open-source instruction set architecture introduced by RISC-V allows large scale customizations in CPU and SoC designs. With this flexibility comes an even larger challenge and dependency on verifying architectural compliance and functional correctness. Since SoC designs nowadays have to compete in a world of significantly increased complexity, multi-million dollar development and manufacturing costs, tight time-to-market constraints, and aggressive competition, the cost and business impact of non production-worthy silicon is extremely high and can be very damaging, even to established major SoC companies. Functional issues at the system level can result into silicon re-spins affecting profitability and time-to-market. In order to counter that, engineering teams need to adopt techniques and tools for verification that scale across the complexity and life-cycle of design. We will here describe STING, a state-of-the-art verification tool for RISC-V based implementations. It embodies a software driven test generation methodology which allows portability of intelligent, self-checking, and architecturally correct test stimulus throughout the life cycle of a design, enabling SoC and IP vendors to achieve their design verification goals quickly and efficiently across pre-silicon, emulation, FPGA and post-silicon phases of development.
Please email email@example.com to set up a meeting at the RISC-V Workshop Barcelona, or to learn more about the verification offerings from Valtrix for RISC-V implementations.
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