Valtrix Systems is happy to announce the availability of STING for RISC-V architecture. RISC-V is an open-source instruction set architecture (ISA) based on reduced instruction set computing (RISC) fundamentals. It has been designed to support extensive customization and specialization across multiple classes of processors. Please note that this is a beta version of STING and we are working on testing and hardening it further. In the sections below, you can find the list of features that are currently implemented in STING and the ones that are going to be supported soon.
The following features are tested and supported in STING at present. These features have been tested on Spike simulator, QEMU model for RISC-V and Rocket core “C++” simulator. (NOTE: Not all the features have been tested on all the models)
Support for the following features are going to be added very soon -
We are very excited about the RISC-V architecture and the potential it holds as an open-source ISA. If you need more information about STING or need a demo, please drop an email to firstname.lastname@example.org
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